 |
| Some main
features of EDWin XP VHDL Editor are : |
| 1. |
It
compiles the source file and generates wirelist
(*.wrs) output file. |
| 2. |
The
output file (*.wrs) may be imported directly into EDWinXP. |
| 3. |
Generates
simulatable models in Mixed Mode & EDSpice Model Generators. |
| 4. |
Converts
the (*.wrs) file to Xilinx,
CUPL
and JEDEC
formats. |
VHDL Editor working is very much similar to
any normal programming editor. All keywords present in the source are highlighted
in Blue. On compiling the error messages will displayed at the
output window below. On double clicking the error the corresponding line
in the editor window will get highlighted in Red. This helps in faster
debugging of source file.
|
